Quantum Weekly: May 18–22, 2026

This issue covers a compressed five-day window — May 17 to 22 — rather than the usual seven. Two events dominate. On May 21, the U.S. Department of Commerce signed $2.013 billion in CHIPS Act letters of intent with nine quantum companies across all five major qubit modalities, anchored by a $1 billion award to a new IBM spin-out called Anderon — America's first pure-play quantum foundry. The same week, IBM's theory team published a route to the teraquop regime using Galois qudit concatenation, and Osaka University's group showed a 22-physical-qubit path to a fault-tolerant CCZ magic state. The lab work and the policy work are, for once, moving at the same pace.

Papers — QEC and fault tolerance

IBM gross code reaches teraquop via Galois qudit concatenation

Field	Detail
arXiv ID	2605.21898
Submitted	May 21, 2026
Institutions	IBM Quantum
Authors	Adam Wills, Michael Beverland, Lev Bishop, Jay Gambetta, Patrick Rall, Vikesh Siddhu, Andrew Cross
Review status	Preprint
Code / data	Not disclosed

Core problem. The gross code is a high-rate quantum LDPC code with attractive hardware properties, but at uniform 10⁻³ physical noise it could not reach the teraquop regime — the threshold at which a single logical qubit requires fewer than one trillion physical operations to fail. High-rate inner codes produce correlated errors that standard concatenation can't decode cleanly. 1

Method. The team treats each inner codeblock as a single logical Galois qudit (a qudit over a Galois field, rather than a two-level qubit). An outer quantum Reed-Solomon code then handles the correlated errors across qudits. A Galois qudit Shor scheme provides fault-tolerant syndrome extraction, and "time-like" Reed-Solomon protects against measurement errors. List decoding closes the circuit.

Results. At uniform 10⁻³ physical noise, the concatenated gross code reaches the teraquop regime with lower space overhead than the 288-qubit two-gross code baseline.

"At uniform 10⁻³ physical noise, the concatenated gross code reaches the teraquop regime, which it previously could not access, with a lower space overhead than the 288-qubit two-gross code, while offering several advantages from the engineering standpoint."
— Wills et al. 1

vs. prior work. Standard concatenation uses low-rate inner codes such as the surface code, where qubit-level transversal gates are available. High-rate inner codes break that assumption. The authors' key finding is that the Galois qudit structure supports lightweight fault-tolerant schemes that have no qubit analogue — suggesting qudit fault-tolerance theory may be structurally distinct from qubit theory, not merely a generalization of it.

Zero-level CCZ distillation: 22 physical qubits for a fault-tolerant magic state

Field	Detail
arXiv ID	2605.21867
Submitted	May 21, 2026
Institutions	Osaka University
Authors	Tomohiro Itogawa, Yutaka Hirano, Yutaro Akahoshi, Keisuke Fujii
Review status	Preprint
Code / data	Not disclosed

Core problem. Magic-state distillation for CCZ gates conventionally requires logical qubits to already be running before distillation begins — a chicken-and-egg overhead that delays practical fault-tolerant computation. The standard 7-T-gate method requires far more physical resources than theoretically necessary.

Method. Itogawa et al. skip the logical-qubit layer entirely. They use the transversal T and T† operations of the [[8,3,2]] code to directly fault-encode a CCZ|+++⟩ state from physical qubits, then teleport it into three surface-code logical qubits via lattice surgery. An adaptively initialized teleportation (AIT) scheme handles the mismatch in code distances between the [[8,3,2]] code and the target surface code. 2

Results. The protocol requires 22 physical qubits, 3 logical qubits, and a circuit depth of 24. Logical error rate: p_L ≃ 300 × p². At p = 10⁻³, this is roughly one order of magnitude better than the 7-T-gate method; at p = 10⁻⁴, roughly two orders of magnitude better.

"The distillation circuit requires only 22 physical qubits, 3 logical qubits, and a circuit depth of 24, reducing the space-time overhead by a factor of approximately 5-10 compared to previous methods."
— Itogawa et al. 2

vs. prior work. Prior magic-state distillation schemes operate at the logical level, requiring a functioning error-corrected substrate first. This "zero-level" approach bypasses that requirement entirely, which matters most for early fault-tolerant machines where qubit budgets are tight.

GeneCS: 85%+ ancilla reduction in code surgery for any stabilizer code

Field	Detail
arXiv ID	2605.21746
Submitted	May 20, 2026
Authors	Junyu Zhou, Ali Javadi-Abhari, Gushu Li
Institutions	Not listed in abstract
Review status	Preprint
Code / data	Not disclosed

Core problem. Code surgery is the standard mechanism for performing logical gates between different quantum error-correcting codes, or between distant logical qubits within the same code. Existing synthesis methods are not structure-aware: they generate far more ancillary qubits and parity checks than necessary, making practical deployment at scale infeasible. 3

Method. GeneCS introduces three optimizations: it eliminates redundant graph nodes during construction, dynamically balances expansion against routing congestion, and enforces code-degree constraints throughout. All three apply to arbitrary stabilizer codes — not just surface codes or specific LDPC families.

Results. Average ancilla and check reduction: over 85%, for both single-code and cross-code logical operations, while preserving logical error rates. Compilation time: approximately 1 second per instance at code sizes up to 10,000 qubits.

"GeneCS achieves an average reduction of over 85% in ancillary qubits and checks for both single-code and cross-code logical operations, while preserving logical error rates."
— Zhou et al. 3

vs. prior work. Existing code surgery compilers work well for surface codes but do not generalize cleanly to the high-rate LDPC codes that are increasingly the target architecture for large-scale fault-tolerant systems. GeneCS's generality is the point.

Papers — Compilers and distributed QC

ATHENA: distributed QC compiler cuts teleportation by 34%, latency by 2×

Field	Detail
arXiv ID	2605.21795
Submitted	May 20, 2026
Institutions	UT Austin + Cisco Quantum Lab
Review status	Preprint
Code / data	Not disclosed

In distributed quantum computers (DQC), a non-local CNOT gate runs 4.3–7.7× slower than a local CNOT and carries roughly 4× higher error rate due to EPR pair consumption. ATHENA introduces two scheduling mechanisms: UMS (Utility-driven Lookahead with Multi-Candidate Block Scheduling) plans teleportations across multiple lookahead blocks simultaneously, and EES (EPR-Capacity-Aware Early Scheduling) fills spare EPR capacity with operations from later blocks before local congestion occurs. 4

"ATHENA reduces teleportations by 34% on average and up to 65%, and reduces latency by 2× on average and up to 2.9× compared to the state-of-the-art."
— Yun et al. 4

FINESSE: fidelity-aware transpilation for tunable-coupler superconducting systems

Field	Detail
arXiv ID	2605.21662
Submitted	May 20, 2026
Institutions	University of Pittsburgh et al.
Target venue	ASPLOS (submitted)
Review status	Preprint
Code / data	Not disclosed

FINESSE co-optimizes frequency allocation and circuit scheduling for SNAIL-coupler (three-wave-mixing coupler) superconducting architectures whose native gate is √iSWAP rather than CNOT. On SNAIL hardware, FINESSE reduces log-infidelity cost by an average of 8.9% and circuit depth by 6.8% relative to SABRE. The paper also benchmarks against IBM Brisbane (CZ-native) and identifies a fidelity–connectivity tradeoff that grows with modular qubit density. 5

dSABRE: 41–44% EPR reduction for multi-core DQC routing

Field	Detail
arXiv ID	2605.21960
Submitted	May 21, 2026
Author	Sanjiang Li (single author)
Review status	Preprint
Code	github.com/ebony72/dsabre

dSABRE adapts SABRE's heuristic routing approach to multi-core DQC. Three additions: a five-term gate-centric teleportation score that includes an explicit capacity-penalty term, a congestion-relief pass that redistributes idle qubits before deadlock, and BFS-layer construction that respects DAG dependence order. On 18 MQT-Bench circuits (25/36/64 logical qubits), dSABRE reduces geometric-mean EPR consumption by 41–44% versus TeleSABRE and by 16–68% versus pytket-dqc. 6 Code is open-sourced.

QuCtrl-BELL: sub-microsecond feedback control for trapped-ion experiments

Field	Detail
arXiv ID	2605.22433
Submitted	May 21, 2026
Institutions	Tsinghua University
Authors	Junpeng She et al. (Luming Duan group)
Review status	Preprint
Code / data	Not disclosed

QuCtrl-BELL is a compiler-driven software stack for real-time trapped-ion control on a RISC-V + PXIe platform. A Python-embedded DSL compiles through six stages — control-flow graph, static single assignment, liveness analysis, graph-coloring register allocation, and instruction scheduling — to hardware FPGA code. A cross-board synchronization protocol achieves feedback-loop latency below 700 ns without host CPU involvement. 7 The paper's core argument: decoupling control-flow state from hardware data-plane state is the key to achieving sub-microsecond feedback while maintaining software modularity.

Papers — Other noteworthy

RL for ion shuttling (Leibniz University Hannover / PTB). Schier et al. apply reinforcement learning to the ion-shuttling scheduling problem on segmented trap chips — the first RL approach to this problem. Shuttling operations reduced by up to 36.3% versus current heuristic methods. The approach transfers across chip architectures, making it a candidate design-phase tool. 8 Preprint.

Adiabatic QPE (MIT, Schmidhuber & Seth Lloyd). Standard gate-based quantum phase estimation (QPE) requires deep controlled time-evolution circuits unsuitable for analog hardware. The proposed adiabatic QPE achieves Heisenberg-limited scaling T = O(ε⁻¹ log(δ⁻¹)) using a single ancilla qubit. By encoding eigenvalues in computational-basis populations rather than complex phases, the protocol is intrinsically robust against certain dephasing errors. 9 Preprint, 6 + 11 pages.

Toshiba QKD detection-mismatch countermeasure (Phys. Rev. Applied). Taylor et al. at Toshiba Europe report the first experimental validation of a four-state countermeasure against detection-efficiency mismatch attacks — a class that includes time-shift attacks — on a GHz-clocked QKD prototype. The countermeasure nearly fully recovers the system's ideal secret key rate. Previously this countermeasure had only a theoretical security proof; this is the hardware demonstration. 10 Published.

QAOA simulation threshold (University of Latvia). Āboliņš and Ambainis prove a sharp interaction-degree threshold for classical simulation of QAOA (quantum approximate optimization algorithm, a heuristic for combinatorial optimization on quantum computers): degree ≥ 3 cost functions make depth-1 QAOA hard to sample classically (polynomial hierarchy collapses to the third level); degree ≤ 2 allows efficient classical exact sampling up to depth O(log n). The important caveat: the hard degree-3 instances have trivially optimizable cost functions, so sampling hardness does not imply quantum optimization advantage. 11 Preprint.

Engineering benchmarks

ParityQC 52-qubit QFT on IBM Heron r3: a routing-free record

A 300mm quantum wafer produced at IBM's facility in Albany, NY — the fabrication platform Anderon will formalize as a standalone foundry — IBM/Anderon: 300mm quantum wafer 12

Researchers from ParityQC (a Vienna-based quantum computing architecture firm) demonstrated a 52-qubit quantum Fourier transform (QFT) on IBM's Heron r3 processor — the largest QFT circuit reported to date, nearly doubling the prior record set in 2024 on trapped-ion hardware. 13

The key technique is "Parity Twine": rather than tracking individual qubit states and inserting SWAP gates to route interactions across the device, the method tracks parity information — the relationships between qubits — and encodes multi-qubit interactions as single-qubit operations on parity strings. This eliminates explicit SWAP routing entirely and improves process fidelity over Qiskit's highly optimized transpiler, particularly at larger circuit sizes.

"It's not about the qubit count. With our method, we were actually able to reduce the errors and still get this doubling."
— Wolfgang Lechner, ParityQC co-founder and co-CEO 13

The QFT is a subroutine inside Shor's algorithm and several quantum simulation workflows. A routing-free, higher-fidelity implementation at 52 qubits is a direct engineering step toward those applications.

Xanadu QROM breakthrough: Toffoli gate count halved

Xanadu announced a two-part algorithmic improvement to quantum read-only memory (QROM) — the standard subroutine for loading classical data onto a quantum computer — cutting the Toffoli gate count by approximately 2×. 14

Toffoli gates (CCX gates) are among the most expensive operations in a fault-tolerant quantum computer because each requires a magic state. The two innovations: replacing qubit-state swapping with a copying mechanism that avoids unnecessary entanglement, and removing redundant data-unload steps when QROM modules appear back-to-back in a circuit. This is the first significant improvement to QROM circuit complexity since approximately 2019. 14

The arXiv preprint is at 2605.20334. Immediate beneficiaries are near-term utility-scale systems where qubit count limits the circuit depth available for data loading — chemistry simulation, optimization, and machine learning applications all rely on QROM-heavy circuits.

The CHIPS Act portfolio

U.S. Department of Commerce CHIPS Act $2B quantum portfolio announcement — Commerce Department seal with quantum hardware visualization — $2.013B quantum computing portfolio, May 21, 2026 15

On May 21, the U.S. Department of Commerce signed non-binding letters of intent (LOIs) with nine quantum companies for a total of $2.013 billion under the CHIPS and Science Act. The government will receive a minority, non-controlling equity stake in each company in exchange — an equity-for-grants mechanism modeled on the earlier Intel semiconductor award. 15

Company	Award	Modality	Focus area
IBM (Anderon)	$1B	Superconducting	300mm quantum wafer foundry, Albany NY
GlobalFoundries	$375M	Multi-modality	Secure quantum foundry for all hardware partners
PsiQuantum	$100M	Photonic	BTO electro-optic switches, high-T single-photon detectors
Quantinuum	$100M	Trapped-ion	Low-loss integrated photonics at ion-trap wavelengths
D-Wave	$100M	Annealing + gate-model	100K-qubit annealing and 10K-qubit gate-model scale-up
Rigetti	Up to $100M	Superconducting	Miniaturized readout electronics, next-gen cryostats
Atom Computing	$100M	Neutral-atom	Scaling arrays to tens of thousands of qubits
Infleqtion	$100M	Neutral-atom	High-power optical systems, error correction
Diraq	Up to $38M	Silicon spin	Spin qubits using standard CMOS process nodes

The commercial logic of the portfolio is deliberate spread: rather than consolidating around one modality, the CHIPS R&D Office funded all five simultaneously. The stated reasoning is that no modality has demonstrated sufficient advantage at scale to bet exclusively on it yet.

"The CHIPS R&D Office is taking a portfolio approach to strengthen and accelerate U.S. leadership across multiple quantum modalities at once, while focusing each award on discrete technological problems of genuine consequence."
— Bill Frauenhofer, Executive Director, CHIPS R&D Office 15

Anderon: IBM's standalone quantum foundry

The single largest award — $1 billion — goes to Anderon, a new IBM subsidiary that will operate an existing 300mm wafer line inside the Albany NanoTech complex. IBM contributes an additional $1 billion in cash, plus IP, assets, and staff. Anderon is structured as a pure-play quantum foundry: it will fabricate superconducting qubit and electronics wafers initially, with plans to add other modalities, and IBM CEO Arvind Krishna confirmed it will offer external customers the same fabrication capability IBM uses internally. 12

"They're going to get the exact same capability that we have for ourselves."
— Arvind Krishna, IBM CEO, to Reuters 16

IBM has deployed over 90 quantum systems globally — more than all other commercial vendors combined — and targets delivery of a large-scale fault-tolerant quantum computer for commercial customers by 2029. 12

The equity mechanism and what's missing from the list

Each LOI is non-binding; final terms are set when definitive agreements are signed. Only GlobalFoundries has disclosed a specific equity figure (approximately 1% strategic stake). D-Wave will issue $100 million in common stock to Commerce upon signing. 17

IonQ (NYSE: IONQ) — by market capitalization the largest publicly traded pure-play quantum company — was not included in the nine. The omission drew commentary from the Financial Times and trade press, though no official explanation has been provided. 18 EE Times also noted that several awarded companies have financial or advisory ties to current Trump administration officials, including PsiQuantum (investor roster includes 1789 Capital, a fund co-led by Donald Trump Jr.) and D-Wave (whose 2022 SPAC was led by current Pentagon official Emil Michael). The Commerce Department describes the selection as based on technical merit and strategic significance; final terms remain under negotiation. 18

Market reaction was immediate. On May 21, D-Wave (QBTS) rose 33%, Infleqtion (INFQ) 31%, Rigetti (RGTI) 30%, IBM 12%, and GlobalFoundries approximately 12%. Several uninvested quantum companies also gained — Arqit (ARQQ) +25%, Quantum Computing Inc. (QUBT) +19%, IonQ +12% — reflecting sectoral sentiment rather than direct awards. Year-to-date through May 21, however, most quantum equities remain sharply down: IBM −24%, RGTI −24%, INFQ −22%, QBTS −26%. 19

Ecosystem — private capital

Quantum Motion $160M Series C. London-based Quantum Motion raised £160 million (approximately $160M) in a Series C co-led by DCVC and Kembara — the largest venture round in UK quantum computing history. 20 The company's approach uses standard CMOS silicon transistors as qubits, which it claims offers a 100× cost and footprint reduction and 1,000× energy reduction versus alternative qubit platforms, and allows deployment in standard data-center racks. British Business Bank and Firgun participated. Total raised to date: over $200M. New investor DCVC also backed Atom Computing, one of the nine CHIPS Act awardees; DCVC Operating Partner Prineha Narang sits on both boards. 20

PsiQuantum at Moreton Bay, Australia. Alongside its CHIPS Act LOI, PsiQuantum announced it will anchor its utility-scale photonic quantum computer at Moreton Bay Central, Queensland — a former paper mill site with existing power infrastructure. 21 Early site works have begun; a formal groundbreaking is scheduled for June 2026. A Test and Validation Lab opens next week at Griffith University's Nathan campus in Brisbane.

A 300mm Barium Titanate (BTO) wafer produced by PsiQuantum in the U.S. — BTO electro-optic switching is the specific technical focus of PsiQuantum's CHIPS Act award — BTO wafer produced by PsiQuantum 22

Xanadu $300M ATM program. Xanadu (Nasdaq: XNDU) announced a $300 million synthetic at-the-market equity program with Yorkville Advisors, giving the company the option (not obligation) to issue and sell up to $300M in Class B subordinate voting shares. 23 This supplements Xanadu's existing $500M+ in total funding.

Quantinuum three-announcement week. Quantinuum ran three announcements in three days: a strategic collaboration with Synopsys (the EDA and engineering simulation software firm) to integrate quantum computing into CFD and electromagnetic simulation workflows for aerospace, life sciences, and semiconductors 24; a joint project with bp targeting seismic imaging for subsurface mapping, where one additional qubit theoretically doubles spatial resolution versus the classical compute-doubling requirement 25; and its CHIPS Act LOI, which specifically targets low-loss integrated photonics for trapped-ion critical wavelengths, with onshore partners GlobalFoundries (cryo-CMOS and 3D interconnect) and Monarch Quantum (integrated photonics). 26

Europe's reaction

The scale of the U.S. commitment triggered immediate concern among European quantum executives. Marta Estarellas, CEO of Barcelona-based Qilimanjaro Quantum Tech, wrote that "Europe is about to give away across the Atlantic the quantum technology it has financed for a decade," arguing that European private capital "broadly still does not understand deep tech" and that policy instruments remain too slow and fragmented to respond at the U.S. pace. 18

Qilimanjaro co-founder Victor Canivell proposed a "quantum Airbus" — consolidating Europe's complementary quantum companies into a single, heavily capitalized entity — and estimated the ratio of U.S. to European VC and PE capital available for deep-tech projects at roughly 100:1. 18 The EU Quantum Flagship program runs to 2028 with a total budget of €1 billion — the same order of magnitude as the IBM award alone. Over $40 billion has been invested globally in quantum computing to date, with North America accounting for roughly 47%, Asia-Pacific 29%, and Europe 15–16%. 18

Conferences

Three quantum computing conferences ran during this window: Q-Expo 2026 in Bilbao (May 18–19), the University of Illinois Quantum Circuit conference (UIQC, May 19–22), and the ICEPP-QUP Quantum Workshop at the University of Tokyo (May 18–19). All three conferences featured sessions on fault-tolerant quantum computing and error correction. None had published proceedings or slides within the five-day window; materials are expected on a two-to-four week delay. 27 28

Cover image: U.S. Department of Commerce CHIPS Act $2B quantum portfolio announcement from Quantum Computing Report